// Copyright (C) 1953-2022 NUDT
// Verilog module name - local_cnt_timing 
// Version: V4.0.0.20221115
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//         global time synchronization 
//         generate report pulse base on global time
///////////////////////////////////////////////////////////////////////////

`timescale 1ns / 1ps

module local_cnt_timing 
(
        i_clk,
        i_rst_n,
        
		o_local_cnt_rst,
        ov_local_cnt
);
// clk & rst
input                  i_clk;
input                  i_rst_n;

output reg             o_local_cnt_rst;
output reg [23:0]      ov_local_cnt;            

always @(posedge i_clk or negedge i_rst_n) begin//local time rst 
    if(!i_rst_n)begin
	    o_local_cnt_rst <= 1'b0;
        ov_local_cnt    <= 24'b0;
    end
    else begin
        ov_local_cnt <= ov_local_cnt + 24'd8;
		if(ov_local_cnt == 24'hfffff8)begin
		    o_local_cnt_rst <= 1'b1;
		end
		else begin
		    o_local_cnt_rst <= 1'b0;
		end
    end
end
endmodule